MIT researchers say nanoscale 3D transistors made from ultrathin semiconductor materials promise more efficient electronics; quantum mechanics offers a path beyond silicon limits

MIT creates nanoscale transistors for efficient electronics
Quantum tunneling delivers low-voltage, high-performance
The technology has the potential to replace silicon

MIT researchers have developed a nanoscale transistor that could potentially pave the way for electronics more efficient than silicon-based devices.

Traditional silicon transistors, critical in most electronic devices, face a physical constraint known as “Boltzmann tyranny,” which prevents them from operating below a certain voltage.

This limitation restricts energy efficiency, especially as modern applications like AI push for faster and more powerful computation.

Nanowire heterostructures

To address these limitations, the MIT team created a new three-dimensional transistor using ultrathin semiconductor materials, including gallium antimonide and indium arsenide.

The design leverages a quantum mechanical phenomenon known as quantum tunneling, allowing electrons to travel through an energy barrier rather than over it. This structure, consisting of vertical nanowires just a few nanometers wide, allows these transistors to operate at much lower voltages while maintaining performance on par with state-of-the-art silicon transistors.

“This is a technology with the potential to replace silicon, so you could use it with all the functions that silicon currently has, but with much better energy efficiency,” Yanjie Shao, an MIT postdoc and lead author of the study, told MIT News. By relying on tunneling transistors, the device achieves a sharp transition between “off” and “on” states with lower voltage, something silicon transistors cannot do as efficiently.

The transistors are engineered using quantum confinement, where electrons are controlled within a tiny space, enhancing their ability to tunnel through barriers. MIT’s advanced facility, MIT.nano, allowed researchers to craft the precise 3D geometry necessary for this effect, creating vertical nanowire heterostructures with diameters as small as 6 nanometers, the tiniest 3D transistors reported to date.

“We have a lot of flexibility to design these material heterostructures so we can achieve a very thin tunneling barrier, which enables us to get very high current,” explains Shao. This design supports a steep switching slope, enabling the device to operate below the voltage limit of conventional silicon.

According to Jesús del Alamo, senior author and Donner Professor of Engineering, “With conventional physics, there is only so far you can go. The work of Yanjie shows that we can do better than that, but we have to use different physics. There are many challenges yet to be overcome for this approach to be commercial in the future, but conceptually, it really is a breakthrough.”

The research team, which includes MIT professors Ju Li, Marco Pala, and David Esseni, has now shifted focus to improving fabrication methods for greater uniformity across chips. Small inconsistencies, even at the nanometer level, can impact device performance, so they are exploring alternative vertical designs that could enhance consistency. The study, published in Nature Electronics, was funded in part by Intel Corporation, reflecting an industry interest in exploring solutions beyond traditional silicon technology.