World’s lowest write power operation for high-speed SOT-MRAM cell achieved

Researchers at the Center for Innovative Integrated Electronic Systems (CIES), Tohoku University, have achieved the world’s lowest write power for a specific type of memory storage device. Not only does this device boast record-breaking energy-efficiency, but it is also incredibly fast. This finding may lead to revolutionary advancements in memory storage device technology that also contribute to a greener, more efficient future.

As technology advances, the demand for high-performance integrated circuits (ICs) that can keep up rises. ICs in current use have a lot of room for improvement, as static random-access memory (SRAM) and dynamic random-access memory (DRAM) consume power even during standby mode.

A potential solution garnering immense global interest is magnetoresistive random-access memories (MRAMs), which take advantage of magnetic properties to maintain high performance without consuming too much power. In particular, spin-orbit-torque magnetoresistive random access memory (SOT-MRAM) holds the potential to outright replace SRAM.

However, SOT-MRAM needs some fine-tuning before we can officially make the switch—namely, improving its energy efficiency at fast writing speeds, and the fact that it needs an external magnetic influence.

To address this, in 2019, a research team at Tohoku University led by Professors Tetsuo Endoh (the director of CIES) and Hideo Ohno (the former president of Tohoku University) demonstrated a canted SOT-MRAM technology with high-speed writing down to 0.35 ns without an assisting external magnetic field.

“Our previous study solved the problem of needing an assisting, external magnetic field,” recounts Endoh. “To further advance this technology to keep up with our fast-paced, AI and Internet-of-Things-based society, the current study was conducted to solve the problem of writing power—the amount of power required to ‘write’ data on the device.”

The research team successfully advanced the design technology for device structure and magnetic properties in canted SOT devices. Specifically, they focused on the tilt angle of the canted SOT device and the magnetic anisotropy of the free layer, using micromagnetic simulation to reduce the write power.

As a result, they achieved the world’s lowest write power of 156 fJ in 75° canted SOT devices fabricated using the 300mm wafer process. They demonstrated that these SOT-MRAM cells reduced the write power (0.35 ns field-free writing) by 35% compared to current SOT device technologies, while still maintaining stability (thermal stability factor (E/k_BT) of 70 and a high TMR ratio of 170%).

These achievements can serve as guidelines for the development of canted SOT-MRAM with low power consumption, high speed, and field-free writing to make SOT-MRAM practical for commercial applications. Based on these findings, adopting SOT-MRAM will contribute to the realization of energy-conscious, high-performance electronics that could launch us into a new era of technological advancements.

Results are being presented at the IEEE International Memory Workshop (IMW 2025), held in Monterey, California, May 18–21, 2025. The paper is titled “Low write power and Field-free sub-ns write speed SOT-MRAM cell with Design Technology of Canted SOT structure and Magnetic Anisotropy for Non-volatile memory.”